SK hynix is redefining the boundaries of memory architecture for AI infrastructure with two breakthrough technologies. At the 2026 OCP Global Summit, the South Korean memory giant unveiled the MARS memory acceleration architecture and HBF high-bandwidth flash technology, targeting the increasingly severe memory bottleneck challenges in AI inference and training.

SK hynix Senior Vice President Hoshik Kim disclosed at the summit that the MARS system can improve time to first token (TTFT) by 3 to 5 times in multi-turn AI inference scenarios, while also significantly compressing tail latency. This performance leap directly addresses the resource imbalance inherent in existing processor-centric cluster architectures, and is expected to reduce the total cost of ownership (TCO) caused by GPU over-provisioning.

Meanwhile, HBF technology expands capacity to 14 times that of HBM while maintaining bandwidth close to HBM levels, with samples planned for early 2028.

The release of these two technologies marks SK hynix opening a differentiated path beyond its main HBM track. Against the backdrop of sustained HBM supply tightness and persistently high demand for high-bandwidth memory from AI chipmakers such as Nvidia, these two technologies could form important complements to existing AI storage architectures and exert a profound impact on the competitive landscape of the memory industry chain.

MARS: Breaking the GPU Over-Provisioning Dilemma Through Memory Disaggregation

Traditional processor-centric distributed computing clusters face structural bottlenecks. Kim noted at the summit that existing architectures have two core deficiencies: first, resource imbalance 鈥?idle memory on one server cannot be easily shared with other nodes; second, rigid scaling 鈥?increasing memory capacity often means purchasing an entirely new server node. The combination of these two problems forces operators to over-provision GPUs, driving up TCO and causing systemic inefficiency.

The core logic of MARS (Memory-Centric AI Rack-Scale System) lies in memory disaggregation. Kim described it as "decoupling memory from traditional CPU/GPU server constraints to build a dedicated large-scale memory pool," thereby achieving a leap from "single-server memory surplus" to "pooled-level efficiency." At the architectural level, MARS further extends this memory tray-level memory pool concept to rack scale, enabling compute and memory to operate collaboratively as shared infrastructure.

In practical application scenarios, the value of MARS is particularly prominent. Kim illustrated with the example of multi-turn AI agent inference services, stating that the system can store the rapidly expanding KV cache in multi-turn conversations within a shared memory system without exhausting GPU memory and storage resources. According to on-site reporting by TrendForce, Kim cited test data showing that compared with recomputation approaches, MARS can achieve 3 to 5 times improvement in TTFT, with tail latency improvement being especially significant.

For AI inference service providers, TTFT is a key metric for measuring user experience, and the compression of tail latency is directly related to service stability in large-scale concurrent scenarios. The GPU over-provisioning problem that MARS targets is also one of the important root causes of persistently high operating costs in current AI data centers.

HBF: Trading Capacity for Architectural Flexibility, Entering Sample Stage in 2028

HBF (High Bandwidth Flash) is another technology track SK hynix is pursuing beyond HBM. Kim clarified at the summit the positioning relationship between HBF and HBM: "HBF extends HBM-level bandwidth to rack-scale capacity... HBF's bandwidth is approximately half of HBM's, but its capacity is approximately 14 times that of HBM."

This positioning reveals HBF's core value proposition: trading a moderate bandwidth concession for significantly expanded capacity space, thereby building a more flexible storage tier at the rack level. For scenarios in large model inference that need to carry massive parameters and context, capacity bottlenecks often constrain system performance more than bandwidth bottlenecks, making HBF's 14x capacity advantage substantively meaningful.

Regarding the technology roadmap, SK hynix released OCP HBF specification version 0.7 in July this year, with version 1.0 expected in early next year, and HBF Cube samples planned for early 2028. This timeline means there is still approximately a two-year window before HBF reaches large-scale commercial deployment, but the continuous advancement of specifications indicates that the industry standardization process is accelerating.

Potential Impact on the AI Chip and Memory Industry Chain

The release of MARS and HBF reflects memory manufacturers' strategic intent to seek diversified breakthroughs against the backdrop of HBM supply tightness. Currently, HBM production capacity is highly concentrated, and strong demand for HBM from AI chipmakers such as Nvidia continues to push up supply pressure, creating market space for alternative or complementary memory architectures.

From a technical logic perspective, MARS does not directly replace HBM, but rather enhances overall memory utilization efficiency at the system architecture level through memory disaggregation, reducing reliance on GPU memory expansion. This means that without increasing HBM procurement volumes, data center operators could potentially improve inference performance by deploying MARS, forming a certain marginal suppressive effect on HBM demand. HBF, meanwhile, provides a capacity supplement to HBM at the storage tier level, helping to alleviate capacity constraints in large model deployment, but its halved bandwidth characteristic determines that it is more suitable as a complementary layer in a tiered storage architecture rather than a direct replacement for HBM.

For the memory industry chain, SK hynix's concentrated release at the OCP Summit is also an important signal to cloud computing vendors and AI infrastructure operators regarding its technology roadmap. As the HBF specification moves toward version 1.0 and enters the sample stage in 2028, ecosystem competition around new memory architectures may unfold ahead of schedule, and the response strategies of competitors such as Samsung and Micron are worth continued attention.